IFE=0, IM=0, OFS=0, CIS=0, PDE=0, OFR=0, KAL=0, KOS=0, KIS=0, IFS=0, COS=0, IFR=0, OFE=0
LTC Control Register
| IM | Interrupt Mask. Once this bit is set, it can only be cleared by hard reset. 0 (0): Interrupt not masked. 1 (1): Interrupt masked |
| PDE | PKHA Register DMA Enable. 0 (0): DMA Request and Done signals disabled for the PKHA Registers. 1 (1): DMA Request and Done signals enabled for the PKHA Registers. |
| IFE | Input FIFO DMA Enable. 0 (0): DMA Request and Done signals disabled for the Input FIFO. 1 (1): DMA Request and Done signals enabled for the Input FIFO. |
| IFR | Input FIFO DMA Request Size 0 (0): DMA request size is 1 entry. 1 (1): DMA request size is 4 entries. |
| OFE | Output FIFO DMA Enable. 0 (0): DMA Request and Done signals disabled for the Output FIFO. 1 (1): DMA Request and Done signals enabled for the Output FIFO. |
| OFR | Output FIFO DMA Request Size 0 (0): DMA request size is 1 entry. 1 (1): DMA request size is 4 entries. |
| IFS | Input FIFO Byte Swap. Byte swap all data that is written to the Input FIFO. 0 (0): Do Not Byte Swap Data. 1 (1): Byte Swap Data. |
| OFS | Output FIFO Byte Swap. Byte swap all data that is read from the Onput FIFO. 0 (0): Do Not Byte Swap Data. 1 (1): Byte Swap Data. |
| KIS | Key Register Input Byte Swap 0 (0): Do Not Byte Swap Data. 1 (1): Byte Swap Data. |
| KOS | Key Register Output Byte Swap 0 (0): Do Not Byte Swap Data. 1 (1): Byte Swap Data. |
| CIS | Context Register Input Byte Swap 0 (0): Do Not Byte Swap Data. 1 (1): Byte Swap Data. |
| COS | Context Register Output Byte Swap 0 (0): Do Not Byte Swap Data. 1 (1): Byte Swap Data. |
| KAL | Key Register Access Lock 0 (0): Key Register is readable. 1 (1): Key Register is not readable. |